Encapsulated power semiconductor assembly

ABSTRACT

The invention relates to an encapsulated power semiconductor assembly comprising a substrate consisting of an insulation material (ceramic), provided with a plurality of islands, which are composed of a thermal conductive material, in particular of partial surfaces of a metal layer. Power semiconductor chips are soldered onto said islands. Electric connections that run from the chips to the connecting elements are produced in the form of bonding pads on additional islands or in the form of wires and islands that are configured as printed conductors. The substrate and the chips are encapsulated, whereas the connection elements project beyond said encapsulation and the metallic underside of the substrate is exposed in order to be fastened to a heat sink.

SCOPE OF THE INVENTION

The invention relates to an encapsulated power semiconductor assembly inwhich a plurality of power semiconductor chips is encapsulated.

STATE OF THE ART

Power semiconductors are being used increasingly in systems where thevoltage is supplied by batteries, particularly in motor manufacture. Atvoltages of 12 to 80 V high currents imposing considerable demands onthe power switches are often generated. In the state of the artencapsulated semiconductor chips are used for switching high currents. Amethod is known for encapsulating several chips simultaneously using aconductor frame, as described for example in DE 26 36 450 C2 and U.S.Pat. No. 4,507,675. The individual power semiconductor components, eachprovided with one chip, are then separated again.

The feed cables to the chips, which depart from connecting elementsprojecting from the enclosure, are often dimensioned, because of theconstruction of the power semiconductor assembly, so that the feedcables exhibit undesirably high resistances, resulting in heatingeffects. Moreover parasitic inductances, resulting in overvoltageeffects, also frequently occur.

An encapsulated power semiconductor assembly, with only one chip, isdescribed in WO 00/07238. Here the chip is applied to a ceramicsubstrate which is coated at the top and bottom with copper. Suchceramic substrates are also referred to as direct-copper-bondsubstrates. They have the advantage that on the one hand the chip iselectrically insulated from the cooling element and on the other thatthe heat is dissipated into the cooling element.

A method is known from EP 0063070 A1 for combining a plurality of powersemiconductor chips. Here two chips, not electrically connected, areapplied to a plate with good thermal conduction and are connected toconnection elements. The heat is dissipated through the plate to abaseplate.

A method is also known for arranging a larger number of components on ametal comb which is embedded with plastic except for one cooling surface(BBC BROWN BOVERI, Power semiconductors, Dr. Heimo Buri, Mannheim 1982).The individual components are then separated again. This embeddingtechnique is used when smaller components are to be manufactured at lowcost in large quantities.

An assembly for diodes, which is provided with a flat aluminium oxidecarrier, which is metallised over part of the surface, is known from DE697 10 885 T2. The diodes are mounted on the metallisation. Contactfaces, which are connected electrically to the diodes by connectingelements which penetrate the carrier, are provided on the side of thecarrier opposite the diodes.

De 196 35 582 C1 describes a power semiconductor component provided witha surface mountable housing, which encloses a chip which is applied to ametal plate.

SUMMARY OF THE INVENTION

The object of the invention is to provide a power semiconductorassembly, which can be manufactured at low cost, with a plurality ofchips which has improved properties, and in particular dissipates heatmore efficiently to the cooling element, in which fewer overvoltages andfewer parasitic inductive effects are generated, and in which the chipscan at least in part be electrically connected to each other.

This object is achieved with the characteristics of claim 1.

Advantageous embodiments of the invention constitute the object of thesub-claims.

Since the chips are placed on thermally conducting islands, preferablyon several islands, and in particular each individual chip is placed ona separate island, the heat from the chips is not transferred to aclosed conductor layer but only to an insulated, i.e. separate area.From this area the heat is then transferred directly into the insulatorsubstrate and can be discharged downwards from this substrate. Forexample, the heat can be transferred to a metal layer which is arrangedon the bottom of the substrate and is not enclosed, i.e. remainsexposed, so that the heat can be discharged onto a cooling element. Theelectrical connections are then heated to a lesser degree or hardly atall.

The thermally and electrically conductive material is preferably ametal, in particular in the form of a thin layer.

The arrangement of the islands, with and without chips, enables theelectrical connections to be optimised. The electrical connections mayinclude soldered connections, (bond) wire connection or even connectionsvia the islands. In optimising the layout of the connecting elementsconsideration may be given to parasitic inductances, e.g. by arrangingconnecting elements conducting a main current adjacent to each other. Toensure that excessively high voltages are not applied to adjacentconnecting elements, the islands are preferably designed so that atleast there is a general tendency for such connecting elements which areprovided with potentials which display a low potential difference(voltage) to be arranged closer to each other than the connectingelements provided with potentials which display a high potentialdifference. The connecting elements may be arranged on two sides, inparticular opposite sides, of the enclosure and project from it. Theyare flat conductor connections which may be bent inside or outside theenclosure. The conductor connections need not all have the samedimensions, nor need they be arranged at the same distance from eachother. For example, they may be narrower on one side of the enclosureand exhibit shorter distances to their nearest neighbour than on theother side of the enclosure. The wider conductor connections on one sideof the enclosure may also be less numerous than the narrow connectionsare on the other side of the enclosure. A slot or recess may be providedin the enclosure underneath the conductor connections for receiving aninsulator, for example a plastic film, so that if there is contactbetween the metallised bottom of the substrate and a heat sink, theconductor connections are separated from the heat sink, to avoidelectrical short-circuits.

In the invention use is made of a metallised ceramic substrate, forexample a direct-copper-bond substrate or a direct-aluminium-bondsubstrate in which the ceramic material may contain aluminium oxideand/or aluminium nitride. The chips may be soldered onto the metalislands.

A plurality of different chips may be used, e.g. MOSFET, diode, IGBTand/or thyristor chips, which may, in their interaction for example,form an individual switch, a chopper, a phase displacer, an H-bridge ora threephase bridge, or a combination of these elements.

BRIEF DESCRIPTION OF THE DRAWING

A preferred embodiment of the invention is described below withreference to a drawing in which:

FIG. 1 shows a diagrammatic internal view of a section of the powersemiconductor assembly according to the invention in a plan view,

FIG. 2 shows a power semiconductor assembly according to the inventionin a plan view,

FIG. 3 shows the power assembly in a bottom view,

FIG. 4 shows a section of the power semiconductor assembly in asectional and enlarged representation, and

FIG. 5 shows a wiring diagram of a combination of six powersemiconductor chips for an embodiment of the invention.

DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION

FIG. 1 shows a view of a power semiconductor assembly in which threeconnecting elements 10 may be seen at the bottom of the figure, andeight connecting elements 12 may be seen opposite at the top of thefigure, which elements 12 are considerably narrower and are closer toeach other than connecting elements 10. Islands, consisting of athermally and electrically conductive insulation material, are locatedon the top of the substrate, which consists of a ceramic insulationmaterial. These islands are formed by a metal layer and are separated bypits 16 which have been produced by etching. The metal layer islandsserve as the electrical connection and for securing connecting elements10 and power semiconductor chips 22.

Upper connecting elements 12 are each connected mechanically andelectrically to adjacent islands 17 on the upper edge of the substrate,and upper connecting elements 10 are connected electrically andmechanically to islands 14 designed as a strip line. Power semiconductorchips 22 are soldered onto islands 21 in the central area of thesubstrate. Furthermore, slightly smaller metal layer islands 19 areprovided between two strip lines 14, which islands serve to bond wireson for electrical connection of the semiconductor chips to theconnecting elements. What is shown, for example, is a bond wire 20 whichleads from a chip 22 to an island 19. A further bond wire 24 then makesthe connection to a connecting element 12 which is in turn connected toan island. A third bond wire 26 is fed from chip 22 via a strip line 14to a connecting element 12. Moreover, the chip is connected by aplurality of adjacent wires 28 to a conductor region 14. The electricalconnections of the other chips are similarly made. The +, − currentconnections are arranged immediately adjacent to each other to reduceinductances, and the current conducting strip lines do not form aconductor loop.

The metal layer is a copper layer which is applied to a relatively thinceramic substrate which is approximately 0.38 mm thin, preferably lessthan 1.0 mm. This suffices as insulation for voltages used in motormanufacture, i.e. voltages which are not too high. On the back theceramic substrate is also coated with copper. A direct-copper-bondsubstrate is therefore used.

FIG. 2 shows the power semiconductor assembly according to the inventionin plan view. The power semiconductor chips are enclosed by a monolithicenclosure 30 of plastic which is pressed around the ceramic substrate.This embedding technique is known to the expert. The enclosure extendsover the entire top of the substrate and engages in the bottom of thesubstrate. Connecting elements 10, 12 project from enclosure 30 in theform of flat conductor connections. In the view of the same powersemiconductor assembly from below, shown in FIG. 3, it is seen that thesubstrate is not fully enclosed by the enclosure but that the lowermetal layer 32 is exposed and is surrounded by a narrow peripheral edge38 of the enclosure. The power semiconductor assembly may therefore beeasily connected to a heat sink. The enclosure recedes on the narrowperipheral edge, forming shoulders 37, so that narrow gaps are formedwhen the semiconductor assembly rests on a cooling element with thelower metal layer (FIG. 4). A flat insulator, which is pushed underneaththe conductor connections, may extend into this gap. The insulator, forexample a small plastic plate, serves to prevent short-circuits betweenthe conductor connections and the cooling element and also to increasethe voltage resistance.

The different chips may be ideally interconnected with the powersemiconductor assembly according to the invention. As an example, FIG. 5shows the connection of six elements as a threephase bridge. Eachelement contains a MOSFET 34 with gate connection G1, G2, G3, G4, G5 andG6, and source connection S1, S2, S3, S4, S5 and S6, as well as a diode36, which may either be part of a MOSFET or may also be separate in theform of a Shottky diode. Otherwise connections not shown here may forman H-bridge or phase displacer.

1. Encapsulated power semiconductor assembly with: a substrate of aceramic insulation material with islands comprising a thermally andelectrically conductive material, at least two power semiconductor chipsarranged on the islands, electrical connections from the chips toconnecting elements, wherein at least two connecting elements areelectrically connected to the islands, wherein an enclosure of pressedplastic material is provided which fully surrounds the powersemiconductor chips and at least partially surrounds the substrate,wherein the connecting elements are designed as flat conductorconnections projecting from the enclosure, and the substrate exhibits ametal coating on a side opposite the islands.
 2. Power semiconductorassembly according to claim 1, wherein the islands include separatepartial surfaces of a metal layer.
 3. Power semiconductor assemblyaccording to claim 1, wherein the substrate is a ceramic substrate whichcontains, aluminium oxide or aluminium nitride ceramic material. 4.Power semiconductor assembly according to claim 1, wherein the metalcoating of the substrate is at least partially exposed on the sideopposite the islands.
 5. Power semiconductor assembly according to claim1, wherein the substrate is a direct-copper-bond ordirect-aluminium-bond substrate.
 6. Power semiconductor assemblyaccording to claim 1, wherein the electrical connections comprisesoldered connections.
 7. Power semiconductor assembly according to claim1, wherein the electrical connections comprise wire connections and/orconnections via the islands.
 8. Power semiconductor assembly accordingto claim 1, wherein the connecting elements are located on two differentsides of the enclosure.
 9. Power semiconductor assembly according toclaim 1, wherein the connecting elements are arranged and connected tothe chips so that connecting elements conducting a main current arearranged adjacent to each other.
 10. Power semiconductor assemblyaccording to claim 1, wherein the connecting elements are arranged andconnected to the chips so that two connecting elements, which areprovided with potentials which have a high mutual potential difference,are arranged further from each other than two connecting elements withpotentials which have a low mutual potential difference.
 11. Powersemiconductor assembly according to claim 1, wherein the chips aresecured to a metal island by means of soldered connections.
 12. Powersemiconductor assembly according to claim 1, wherein at least oneshoulder is formed on a bottom of the enclosure for inserting a flatinsulator.
 13. Power semiconductor assembly according to claim 1,wherein the chips comprise MOSFET, diode, IGBT and/or thyristor chips.14. Power semiconductor assembly according to claim 1, wherein thechips, when interacting, form an individual switch, a chopper, a bridgebranch, an H-bridge or a threephase bridge or a combination of theseelements.